In logic circuit design, it is sometimes necessary to insert level restoration circuitry into a circuit to restore a signal to a valid logic level. For example, a very long routing path in an integrated circuit can degrade a high logic signal due to the impedance of the routing trace. Heavily loaded lines can also degrade a valid logic high signal. This problem also occurs in pass-gate logic designs that include a number of transistors coupled in series because of the threshold voltage drop across the transistors.
Serial pass-gate logic refers to logic circuits where logical functions are implemented using a network of pass-gates coupled in series. FIG. 1 is a schematic diagram illustrating an example of a pass-gate string 20 coupled to an inverter 22. The term, "pass-gate" refers to the manner in which a gate in the logic network passes a logic signal from an input to an output when the gate is turned on. For example, FIG. 1 illustrates a string of four pass-gates 24-30 coupled in series. In order for the logic signal to pass from the input of the first pass-gate 24 to the output of the fourth pass-gate 30, each of the four pass-gates must be turned on.
Logic functions may be constructed from a network of pass-gates to produce a desired output in response to one or more inputs. When pass-gates are constructed of N-channel transistors coupled in series, it is sometimes difficult to produce valid logic signals at the output of the pass-gate network. Consider, for example, the pass-gate network illustrated in FIG. 1. This particular pass-gate network is able to produce a valid logic zero level, but it cannot produce a valid logic one level. The signal level is degraded because of the threshold voltage drop across each of the four pass-gates 24-30 coupled in series. Assuming a threshold voltage drop of one volt across the pass-gate string 20 and a supply voltage of 3 volts, the output of the N-channel pass-gate string will swing from about zero volts to about 2 volts. This output voltage swing is insufficient to reliably drive other logic stages coupled to the output of the pass-gate network.
Specifically in this case, the voltage swing produced by the pass-gate string is insufficient to reliably drive the inverter 22 coupled to the output of the pass-gate network. As a result, the P-channel transistor 32 in the inverter does not completely turn off when the logic signal at 2 volts is applied to the input. The failure of the P-channel transistor 32 to turn off can cause excessive static current to flow through the inverter and attenuate its output swing.
One possible solution is to increase the supply voltage. However, this alternative is unsatisfactory because the trend in the industry is toward lower power devices that operate at lower supply voltages. Increasing the supply voltage is contrary to this trend and results in higher power consumption.
Another possible solution is to use a pull-up transistor connected as shown in FIG. 2. FIG. 2 is a schematic diagram of an N-channel pass-gate network 40 with a P-channel pull-up transistor 42. In this example, the P-channel pull-up transistor 42 is added to address the insufficient gate drive problem. The P-channel pull-up transistor 42 is driven by the output 44 of the inverter 46 and is designed to pull-up the output of the pass-gate network 40 to a valid logic signal. The P-channel transistor 42 coupled to the output of the inverter 46 forms a feedback path that detects the N-channel transistor 48 in the inverter turning on, and in response ensures that the P-channel transistor 50 in the inverter turns off.
When used in conjunction with an N-channel pass-gate network as shown in FIG. 2, the pull-up transistor 42 addresses the gate drive problem sufficiently at low frequencies. However, as the frequency increases, the P-channel pull-up transistor 42 cannot turn on fast enough to pull-up the output of the pass-gate network 40 to a valid logic signal. As a result, the signal swing at the input of the inverter 46 decreases, and eventually reaches an insufficient voltage swing from zero to 2 volts.
When a small pull-up transistor is used is relative to the N-channel devices in the pass-gate string, the source impedance of the pull-up transistor 42 is higher. As such, the pull-up transistor 42 cannot provide sufficient current to pull-up the transistors in the pass-gate string 40. The larger N-channel devices have a higher parasitic capacitance relative to the pull-up transistor, and thus, are more difficult to pull-up to a logic high level.
One solution to this problem is to increase the size of the pull-up transistor. This is an unsatisfactory solution, however, because it causes the logic level zero signal to the inverter to be degraded. The pass-gate string 40, due to its high resistance value, cannot source zero volts while the pull-up transistor 42 is active. The pass-gate string current must overcome the current sourced by the pull-up transistor 42 to achieve a logic zero value.
The problem with the pull-up transistor 42 in FIG. 2 is especially a concern when the speed of the N-channel and P-channel transistors is not matched. When the P-channel is faster than the N-channel devices in the string, it is more difficult for the N-channel devices to provide a valid logic low. In this case, the impedance of the pass-gate string is higher, making it more difficult for the string to sink current. When the N-channel devices are faster than the P-channel devices, it is more difficult for the P-channel device to source current and pull-up the output of the string to a logic high level.
As is apparent from the foregoing discussion, there is a need for an improved restoration circuit for insuring valid logic signals in pass-gate networks.